Verisity and eInfochips Meeting Demand For eVCs

MOUNTAIN VIEW, CA -- May 28, 2002 Verisity, Ltd. (Nasdaq: VRST), the leading provider of functional verification automation tools, and eInfochips Inc., today announced the availability of three new e Verification Components (eVCs™) from eInfochips: Fibre Channel, SONET and Gigabit Ethernet. eVCs are configurable, reusable plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. These eVCs, which were developed using Specman Elite™, significantly reduce the time necessary to create the verification infrastructure and automated testbench environment required for verifying today’s DSM designs and complex SoCs.

“eInfochips is a proud member of Verisity’s Verification Alliance™ program. Today’s announcement demonstrates not only our commitment to the Verification Alliance program but our leadership position as well,” said Pratul Shroff, President and CEO of eInfochips. “By seamlessly integrating our long-time expertise in verifying complex SoC designs with Verisity's excellent directed and random-based verification methodologies, we have come up with reliable eVCs, pre-verified to the standard Fibre Channel, SONET and Gigabit Ethernet protocols. These eVCs and our network of experts trained on leading verification technologies will provide a wider range to access and enhance verification productivity.“The Verification Alliance program has been a great resource for our customers for both additional consulting services and eVCs,” said Dave Tokic, director of strategic marketing for Verisity. “eInfochips has taken a leadership position within Verification Alliance, with its strong dedication to Specman Elite and eVC development. The eVCs for Fibre Channel, SONET and Gigabit Ethernet are a critical component of verification environments for any design containing these standards.”

About Fibre Channel eVC
The Fibre Channel eVC is fully compliant with the FC-PH standards from ANSI and supports Point-to-Point and Fabric topologies, Loop-back mode and Basic Link Services. It includes configurable pattern generator for injecting random, directed-random, as well erroneous test cases and supports the scoreboard implementation. With it’s support for accumulated coverage as well as extensive coverage for individual test cases, which are fully compliant with the FC-PH standards from ANSI, it ensures the thorough checking of Fibre Channel layers viz. FC-0, FC-1 and part of FC-2.

About SONET eVC
The SONET eVC is compliant to the ANSI T1.105 standard. It comprises of STS-1 frame and supports configurable payload mapping and concatenated STS-N frame generation. Apart from supporting deterministic and random payload generation for ATM & DSx mapping, it has provision for Virtual Tributary (VT) grouping for DSx as well as custom payload and On-the-fly Transport Over Head (TOH) and Path Over Head (POH) configuration. Configurable frame scrambling engine, AIS Protocol Checking, event generation and parity calculation with/without error as per configuration, are also included in the SONET eVC.

About Gigabit Ethernet eVC
The Gigabit Ethernet eVC is compliant to ISO/IEC 8802-3:2000(E) and IEEE Draft P802.3ae/D4.0 specifications. It supports the management interface for XGMII, RGMII, GMII, RMII, MII. It includes extensible coverage collection and supports scoreboard checking of input/output. The Gigabit Ethernet eVC supports configuration of multiple ports and utilizes the latest �plug & play’ eVC methodology to ensure full compatibility and inter-operability with other eVCs.

For complete features of the Fibre Channel eVC, SONET eVC and Gigabit Ethernet eVC, please contact parag@einfochips.com

e Verification Components
eVCs foster verification reuse because they can easily be moved from the module-level verification to SoC-level verification, as well as from one chip design to another. Users can drop them into their designs and drastically cut the time it takes to create a verification environment.

Each eVC includes three integrated components: a stimuli generator for injecting and generating traffic, monitors and checkers for viewing outputs and checking protocol rules, and coverage reports showing the functional coverage of scenarios. They can be used in a variety of design applications and are available for a wide array of industry standards.

For a complete listing of eVCs available, please visit http://www.verisity.com and customers can log in to http://www.verificationvault.com.

Availability
The Fibre Channel, SONET and Gigabit Ethernet eVCs work with Verilog and VHDL devices and simulators that are supported by Specman Elite and will be available starting June 2002. These eVCs come with complete documentation and example configurations for typical verification environments.

About eInfochips eInfochips has a large team of engineers, between India and USA, which is highly competent in advanced verification and has long time experience in verifying complex ASICs, IP/Cores, System-on-Chip and custom ICs. With a commitment to work extensively with high-level verification languages (HVL) and to leverage the power of automation tools, eInfochips has become a spearhead in the automated verification methodologies’ domain.

Not only does the company deliver high-quality services based on superior verification methodologies, but is also dedicated to design and develop e HVL and Specman Elite (testbench automation tool) based, reusable Verification Components -- eVCs, that are pre-verified, greatly configurable & extensible and yield higher quality results at the verification task.

eInfochips' high-level Specman Elite expertise and eVCs, assist design and verification engineers to come up with their verification environments, with maximum efficiency in the shortest time, and this dramatic reduction in the time-to-verify enables the clients to compete effectively in their target markets and to widen their customer base.

eInfochips has chosen the route of partnership with cutting edge technology companies to meet the ever-emerging needs of customer for the design and verification services. For more information on eInfochips visit http://www.einfochips.com or write to us at parag@einfochips.com

About Verisity Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to high growth segments of the electronics industry. Verisity’s products automate the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.

Verisity Design, Inc.'s principal executive offices are located in Mountain View, CA. The Company's principal research and development offices are located in Rosh Ha'ain, Israel. For more information, see Verisity's web site at www.verisity.com.

For more information contact:
Jennifer Bilsey
Verisity Design, Inc.
(650) 934-6823
jen@verisity.com